The present invention relates to a data processing device on an integrated circuit (IC) chip, such as a micro processor, and more particularly to a word access structure for memory blocks or registers provided in the data processing chip.
Data processing chips have been widely utilized in various data or information processing fields. A plurality of memory blocks or registers are provided in the data processing chip, and each of the memory blocks or registers is assigned by it's own word. A decoder circuit is employed to select one of the words so that one of the memory blocks or registers is selected by the selected word. In the case where the number of the words, i.e. the number of memory blocks or registers are 256, the decoder receives 8-bit of address signals and 256 memory selection lines are derived from the decoder to the memory blocks or registers. However, the memory blocks or registers are usually located at different portions on the chip according to their functions in the data processing device, whereas the decoder circuit for selecting one of the 256 memory selection lines is provided at a certain location. Accordingly, the 256 memory selection lines are inevitably running between the decoder circuit and the respective memory blocks on the data processing chip, thus occupying a large area on the chip. Therefore, it has been difficult to obtain a data processing chip having a high-integration density.